Field of the Invention
The present invention relates in general to prefetching information into a cache memory, and more particularly to a stride reference prefetcher that determines a minimum stride value and stride direction between successive load accesses for identifying at least one prefetch address.
Description of the Related Art
Memory access latency is a significant factor in reducing processing performance and efficiency. Processing circuitry is often separated from a primary memory through multiple layers of circuitry and associated access protocols. For example, a processor may be coupled to an external system memory that stores information needed by the processor, such as instructions and data and other information to be processed by a computer system. Access to the external system memory may be relatively slow since the information must often traverse multiple levels of circuitry, such as a bus interface unit and/or a memory controller and the like, and the external devices often operate with a slower system clock. A processor typically incorporates at least one level of cache memory that locally stores information retrieved from the external system memory for faster access by processing circuitry within the processor. Access to an internal cache is substantially faster since the cache is physically closer, has fewer intermediate circuitry levels, and often operates at a faster clock speed.
Prefetching is a commonly used technique in which blocks of information are retrieved from the primary memory in advance and stored into a local cache for faster access by the processing circuitry when needed. Although the cache memory may be significantly faster, performance and efficiency are improved only when the cache retrieves the information that is subsequently requested by the processing circuitry in a timely fashion. A prefetching algorithm that does not retrieve the target information or otherwise retrieves too much of the wrong information may not appreciably increase and may even reduce overall performance and efficiency.